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| 1 pin configurations features ? low pin count (lpc) bios device functions as firmware hub for intel 810, 810e, 820, 840 chipsets 8m or 4m bits of flash memory for platform code/data storage ? uniform, 64-kbyte memory sectors ? available in 8m bits (AT49LW080) and 4m bits (at49lw040) ? automated byte-program and sector-erase operations two configurable interfaces ? firmware hub (fwh) interface for in-system operation ? address/address multiplexed (a/a mux) interface for programming during manufacturing firmware hub hardware interface mode ? 5-signal communication interface supporting x8 reads and writes ? read and write protection for each sector using software-controlled registers ? two hardware write-protect pins: one for the top boot sector, one for all other sectors ? five general-purpose inputs, gpis, for platform design flexibility ? operates with 33 mhz pci clock and 3.3v i/o address/address multiplexed (a/a mux) interface ? 11-pin multiplexed address and 8-pin data interface ? supports fast on-board or out-of-system programming power supply specifications ?v cc : 3.3v 0.3v ?v pp : 3.3v and 12v for fast programming industry-standard packages ? (40-lead tsop or 32-lead plcc) description the AT49LW080 and the at49lw040 are flash memory devices designed to be com- patible with the intel 82802ac and the intel 82802ab firmware hub (fwh) devices for pc-bios application. a feature of the AT49LW080/040 is the nonvolatile memory core. the high-performance memory is arranged in eight (at49lw040) or sixteen (AT49LW080) 64-kbyte sectors (see page 13). 8-megabit and 4-megabit firmware hub flash memory AT49LW080 at49lw040 plcc 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 [a7] fgpi1 [a6] fgpi0 [a5] wp [a4] tbl [a3] id3 [a2] id2 [a1] id1 [a0] id0 [i/o0] fwh0 ic (v il ) [ic(v ih )] gnda [gnda] vcca [vcca] gnd [gnd] vcc [vcc] init [oe] fwh4 [we] rfu [ry/by] rfu [i/o7] 4 3 2 1 32 31 30 14 15 16 17 18 19 20 [i/o1] fwh1 [i/o2] fwh2 [gnd] gnd [i/o3] fwh3 [i/o4] rfu [i/o5] rfu [i/o6] rfu fgpi2 [a8] fgpi3 [a9] rst [rst] vpp [vpp] vcc [vcc] clk [r/c] fgpi4 [a10] [ ] designates a/a mux mode tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (nc) nc [ic (v ih )] ic (v il ) [nc] nc [nc] nc [nc] nc [nc] nc [a10] fgpi4 [nc] nc [r/c] clk [vcc] vcc [vpp] vpp [rst] rst [nc] nc [nc] nc [a9] fgpi3 [a8] fgpi2 [a7] fgpi1 [a6] fgpi0 [a5] wp [a4] tbl gnda [gnda] vcca [vcca] fwh4 [we] init [oe] rfu [ry/by] rfu [i/o7] rfu [i/o6] rfu [i/o5] rfu [i/o4] vcc [vcc] gnd [gnd] gnd [gnd] fwh3 [i/o3] fwh2 [i/o2] fwh1 [i/o1] fwh0 [i/o0] id0 [a0] id1 [a1] id2 [a2] id3 [a3] [ ] designates a/a mux mode rev. 1966c?flash?03/02
2 AT49LW080/040 1966c?flash?03/02 the AT49LW080/040 supports two hardware interfaces: firmware hub (fwh) for in- system operation and address/address multiplexed (a/a mux) for programming during manufacturing. the ic (interface configuration) pin of the device provides the control between the interfaces. the interface mode needs to be selected prior to power-up or before return from reset (rst or init low to high transition). an internal command user interface (cui) serves as the control center between the two device interfaces (fwh and a/a mux) and internal operation of the nonvolatile memory. a valid command sequence written to the cui initiates device automation. specifically designed for 3v systems, the AT49LW080/040 supports read operations at 3.3v and sector erase and program operations at 3.3v and 12v v pp .the12vv pp option renders the fastest program performance which will increase factory throughput, but is not recommended for standard in-system fwh operation in the platform. with the 3.3v v pp option, v cc and v pp should be tied together for a simple, low-power 3v design. in addition to the voltage flexibility, the dedicated vpp pin gives complete data protec- tion when v pp v pplk . internal v pp detection circuitry automatically configures the device for sector erase and program operations. note that, while current for 12v pro- gramming will be drawn from v pp , 3.3v programming board solutions should design such that v pp draws from the same supply as v cc , and should assume that full program- ming current may be drawn from either pin. firmware hub interface the firmware hub (fwh) interface is designed to work with the i/o controller hub (ich) during platform operation. the fwh interface consists primarily of a five-signal communication interface used to control the operation of the device in a system environment. the buffers for this inter- face are pci compliant. to ensure the effective delivery of security and manageability features, the fwh interface is the only way to get access to the full feature set of the device. the fwh interface is equipped to operate at 33 mhz, synchronous with the pci bus. address/address multiplexed interface the a/a mux interface is designed as a programming interface for oems to use during motherboard manufacturing or component pre-programming. the a/a mux refers to the multiplexed row and column addresses in this interface. this approach is required so that the device can be tested and programmed quickly with automated test equipment (ate) and prom programmers in the oem?s manufacturing flow. this interface also allows the device to have an efficient programming interface with potentially large future densities, while still fitting into a 32-pin package. only basic reads, programming, and erase of the nonvolatile memory sectors can be performed through the a/a mux interface. in this mode fwh features, security features and regis- ters are unavailable. a row/column (r/c ) pin determines which set of addresses ?rows or columns? are latched. 3 AT49LW080/040 1966c?flash?03/02 block diagram pin description table 1 details the usage of each of the device pins. most of the pins have dual function- ality, with functions in both the firmware hub and a/a mux interfaces. a/a mux functionality for pins is shown in bold in the description box for that pin. all pins are designed to be compliant with voltage of v cc + 0.3v max, unless otherwise noted. fwh interface a10 - a0 i/o7 - i/o0 flash array control logic a/a mux interface rst ic clk fwh (4:0) id (3:0) fgpi (4:0) tbl wp we r/c oe init ry/by table 1 . pin description symbol type interface name and function fwh a/a mux ic input x x interface configuration pin: this pin determines which interface is operational. this pin is held high to enable the a/a mux interface. this pin is held low to enable the fwh interface. this pin must be set at power-up or before return from reset and not changed during device operation. this pin is pulled down with an internal resistor, with value between 20 and 100 k ? . with ic high (a/a mux mode), this pin will exhibit a leakage current of approximately 200 a. this pin may be floated, which will select fwh mode. rst input x x interface reset: valid for both a/a mux and fwh interface operations. when driven low, rst inhibits write operations to provide data protection during power transitions, resets internal automation, and tri-states pins fwh [3:0] (in fwh interface mode). rst high enables normal operation. when exiting from reset, the device defaults to read array mode. init input x processor reset: this is a second reset pin for in-system use. this pin is internally combined with the rst pin. if this pin or rst is driven low, identical operation is exhibited. this signal is designed to be connected to the chipset init signal (max voltage depends on the processor. do not use 3.3v.) a/a mux = oe 4 AT49LW080/040 1966c?flash?03/02 clk input x 33 mhz clock for fwh interface: this input is the same as the pci clock and adheres to the pci specification. a/a mux = r/c fwh[3:0] i/o x fwh i/os: i/o communication. a/a mux = i/o[3:0] fwh4 input x fwh input: input communication. a/a mux = we id[3:0] input x identification inputs: these four pins are part of the mechanism that allows multiple parts to be attached to the same bus. the strapping of these pins is used to identify the component. the boot device must have id[3:0] = 0000 and it is recommended that all subsequent devices should use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.). these pins are pulled down with internal resistors, with values between 20 and 100 k ? when in fwh mode. any id pins that are pulled high will exhibit a leakage current of approximately 200 a. any pins intended to be low may be left to float. in a single fwh system, all may be left floating. a/a mux = a[3:0] fgpi[4:0] input x fwh general purpose inputs: these individual inputs can be used for additional board flexibility. the state of these pins can be read through fwh registers. these inputs should be at their desired state before the start of the pci clock cycle during which the read is attempted, and should remain at the same level until the end of the read cycle. they may only be used for 3.3v signals. unused fgpi pins must not be floated. a/a mux = a[10:6] tbl input x top sector lock: when low, prevents programming or sector erase to the highest addressable sector (7 in a 4-mbit, 15 in an 8-mbit component) regardless of the state of the lock registers tbl high disables hardware write protection for the top sector, though register-based protection still applies. the status of tbl does not affect the status of sector-locking registers. a/a mux = a4 wp input x write-protect: when low, prevents programming or sector erase to all but the highest addressable sectors (0 - 6 in a 4-mbit, 0 - 14 in an 8-mbit component), regardless of the state of the corresponding lock registers. w p-high disables hardware write protection for these sectors, though register-based protection still applies. the status of tbl does not affect the status of sector-locking registers. a/a mux = a5 a0 - a10 input x low-order address inputs: inputs for low-order addresses during read and write operations. addresses are internally latched during a write cycle. for the a/a mux interface these addresses are latched by r/c and share the same pins as the high-order address inputs. table 1 . pin description (continued) symbol type interface name and function fwh a/a mux 5 AT49LW080/040 1966c?flash?03/02 i/o0 - i/o7 i/o x data input/outputs: these pins receive data and commands during write cycles and transmit data during memory array and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. oe input x output enable: gates the device?s outputs during a read cycle. r/c input x row-column address select: for the a/a mux interface, this pin determines whether the address pins are pointing to the row addresses, a0 - a10, or to the column addresses, a11 - a18 (at49lw040) or a11 - a19 (AT49LW080). we input x write enable: controls writes to the array sectors. addresses and data are latched on the rising edge of the we pulse. v pp supply x x sector erase/program power supply: for erasing array sectors or programming data. v pp = 3.3v or 12v. with v pp v pplk , memory contents cannot be altered. sector erase or program with an invalid v pp (see dc characteristics) produces spurious results and should not be attempted. v pp may only be held at 12v for 80 hours over the lifetime of the device. v cc supply x x device power supply: internal detection automatically configures the device for optimized read performance. do no float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltages (see dc characteristics) produce spurious results and should not be attempted. gnd supply x x ground: do not float any ground pins. v cca supply x x analog power supply: this supply should share the same system supply as v cc . gnda supply x x analog ground: should be tied to same plane as gnd. rfu x reserved for future use: these pins are reserved for future generations of this product and should be connected accordingly. these pins may be left disconnected or driven. if they are driven, the voltage levels should meet v ih and v il requirements. a/a mux = i/o[7:4] nc x x no connect: pin may be driven or floated. if it is driven, the voltage levels should meet v ih and v il . no connects appear only on the 40-lead tsop package. ry/by output x ready/busy: valid only in a/a mux mode. this output pin is a reflection of bit 7 in the status register. this pin is used to determine sector erase or program completion. table 1 . pin description (continued) symbol type interface name and function fwh a/a mux 6 AT49LW080/040 1966c?flash?03/02 firmware hub interface (fwh) table 2 lists the seven required signals used for the fwh interface. fwh[3:0]: the fwh[3:0] signal lines communicate address, control, and data informa- tion over the lpc bus between a master and a peripheral. the information communicated are: start, stop (abort a cycle), transfer type (memory, i/o, dma), trans- fer direction (read/write), address, data, wait states, dma channel, and bus master grant. fwh4: fwh4 is used by the master to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. this signal is to be used be by peripherals to know when to monitor the bus for a cycle. the fwh4 signal is used as a general notification that the fwh[3:0] lines contain infor- mation relative to the start or stop of a cycle, and that peripherals must monitor the bus to determine whether the cycle is intended for them. the benefit to peripherals of fwh4 is, it allows them to enter lower power states internally. when peripherals sample fwh4 active, they are to immediately stop driving the fwh[3:0] signal lines on the next clock and monitor the bus for new cycle information. reset: rst or init at vil initiates a device reset. in read mode, rst or init low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. rst or init must be held low for time t plph (a/a mux and fwh opera- tion). the fwh resets to read array mode upon return from reset, and all sectors are set to default (locked) status regardless of their locked state prior to reset. driving rst or init low resets the device, which resets the sector lock registers to their default (write-locked) condition. a reset time (t phqv a/a mux) is required from rst or init switching high until outputs are valid. likewise, the device has a wake time (t phrh a/a mux) from rst or init high until writes to the cui are recognized. a reset latency will occur if a reset procedure is performed during a programming or erase operation. during sector erase or program, driving rst or init low will abort the operation under- way, in addition to causing a reset latency. memory contents being altered are no longer valid, since the data may be partially erased or programmed. it is important to assert rst or init during system reset. when the system comes out of reset, it will expect to read from the memory array of the device. if a system reset occurs with no fwh reset (this will be hardware dependent), it is possible that proper cpu ini- tialization will not occur (the fwh memory may be providing status information instead of memory array data). ta ble 2. fwh required signal list signal direction description peripheral master fwh[3:0] i/o i/o multiplexed command, address and data fwh4 i o indicates start of a new cycle, termination of broken cycle. rst i i reset: same as pci reset on the master. the master does not need this signal if it already has pcirst on its interface. clk i i clock: same 33 mhz clock as pci clock on the master. same clock phase with typical pci skew. the master does not need this signal if it already has pciclk on its interface. 7 AT49LW080/040 1966c?flash?03/02 cycle types: there are two types of cycles that are supported by the AT49LW080/040: fwh memory read and fwh memory write. fwh memory read or write cycles start with a preamble. preamble: the preamble consists of a start, idsel, 28-bit address and msize fields. the preamble is shown in figure 1. the preamble begins with fwh4 going low andastartfielddrivenonfwh[3:0].forfwhmemoryreadcycles,thestartfield must be 1101b; for fwh memory write cycles, the start field must be 1110b. follow- ing the start field is the idsel field. this field acts like a chip select in that it indicates which device should respond to the current transaction. the next seven clocks are the 28-bit address, which tell from where to begin reading or writing in the selected device. next, an msize value of 0 indicates the master is requesting a single byte. figure 1. fwh memory cycle preamble start: this one-clock field indicates the start of a cycle. it is valid on the last clock that fwh4 is sampled low. the two start fields that are used for the cycle are shown in table 3. if the start field that is sampled is not one of these values, then the cycle attempted is not an fwh memory cycle. it may be a valid memory cycle that the fwh component may wish to decode, i.e., it may be of the lpc memory cycle variety. idsel (device select): this one-clock field is used to indicate which fwh compo- nent is being selected. the four bits transmitted over fwh[3:0] during this clock are compared with values strapped onto pins [id3:id0] on the fwh component. if there is a match, the fwh component will continue to decode the cycle to determine which bytes are requested on a read or which bytes to update on a write. if there isn?t a match, the fwh component may discard the rest of the cycle and go into a standby power state. maddr (memory address): this is a seven-clock field, which gives a 28-bit mem- ory address. this allows for up to 256 mb per memory device, for a total of a 4 gb addressable space. the address is transferred with the most significant nibble first. msize (memory size): ?0000b? will be sent in this field. a value of ?0000b? corre- spondstoasinglebytetransfer. ta ble 3. start fields fwh[3:0] indication 1101b fwh memory read 1110b fwh memory write clk fwh4 fwh3 - fwh0 start idsel msize 28-bit address 8 AT49LW080/040 1966c?flash?03/02 device operation read: read operations consist of preamble, tar, sync and data fields as shown in figure 2 and described in table 5. tar and sync fields are described below. com- mands using the read mode include the following functions: reading memory from the array, reading the identifier codes, reading the lock bit registers and reading the gpi registers. memory information, identifier codes, or the gpi registers can be read inde- pendent of the v pp voltage. upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. read cycle, single byte: for read cycles, after the preamble, the master drives a tar field to give ownership of the bus to the fwh. after the second clock of the tar phase the fwh assumes the bus and begins driving sync values. when it is ready, it drives the low nibble, then the high nibble of data, followed by a tar field to give control back to the master. figure 2 shows a device that requires three sync clocks to access data. since the access time can begin once the address phase has been completed, the two clocks of the tar phase can be considered as part of the access time of the part. for example, a device with a 120 ns access time could assert ?0101b? for clocks 1 and 2 of the sync phase and ?0000b? for the last clock of the sync phase. this would be equivalent to five clocks worth of access time if the device started that access at the conclusion of the preamble phase. once sync is achieved, the device then returns the data in two clocks and gives ownership of the bus back to the master with a tar phase. turn-around (tar): this field is two clocks wide, and is driven by the master when it is turning control over to the fwh, (for example, to read data), and is driven by the fwh when it is turning control back over to the master. on the first clock of this two-clock-wide field, the master or fwh drives the fwh[3:0] lines to ?1111b?. on the second clock of this field, the master or peripheral tri-states the fwh[3:0] lines. sync: this field is used to add wait states. it can be several clocks in length. on target or dma cycles, this field is driven by the fwh. if the fwh needs to assert wait states, it does so by driving ?0101b? (short sync) on fwh[3:0] until it is ready. when ready, it will drive ?0000b?. valid values for this field are shown in table 4. figure 2. fwh single-byte read waveforms ta ble 4. valid sync values bits[3:0] indication 0000 ready: sync achieved with no error. 0101 short wait: part indicating wait states. idsel maddr msize tar sync(3) tar data clk fwh4 fwh[3:0] preamble start 9 AT49LW080/040 1966c ? flash ? 03/02 note: 1. field contents are valid on the rising edge of the present clock cycle. table 5 . fwh read cycle clock cycle field name field contents (1) fwh[3:0] fwh[3:0] direction comments 1 start 1101b in fwh4 must be active (low) for the part to respond. only the last start field (before fwh4 transitioning high) should be recognized. the start field contents indicate an fwh memory read cycle. 2 idsel 0000b to 1111b in indicates which fwh device should respond. if the idsel (id select) field matches the value id[3:0], then that particular device will respond to subsequent commands. 3 - 9 maddr yyyy in these seven clock cycles make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most significant nibble first. 10 msize 0000b (1 byte) in the fwh will only support single-byte transfers. 11 tar0 1111b in then float in this clock cycle, the master (ich) has driven the bus to all 1s and then floats the bus, prior to the next clock cycle. this is the first part of the bus ? turnaround cycle ? . 12 tar1 1111b (float) float then out the fwh takes control of the bus during this cycle. during the next clock cycle, it will be driving ? sync data ? . 13 - 14 wsync 0101b (wait) out the fwh outputs the value 0101, a wait-sync (wsync, a.k.a. ? short-sync ? ), for two clock cycles. this value indicates to the master (ich) that data is not yet available from the part. this number of wait- syncs is a function of the device ? s access time. 15 rsync 0000b (ready) out during this clock cycle, the fwh will generate a ? ready-sync ? (rsync) indicating that the least significant nibble of the least significant byte will be available during the next clock cycle. 16 data yyyy out yyyy is the least significant nibble of the least significant data byte. 17 data yyyy out yyyy is the most significant nibble of the least significant data byte. 18 tar0 1111b out then float the fwh flash memory drives fwh0 - fwh3 to 1111b to indicate a turnaround cycle. 19 tar1 1111b (float) float then in the fwh flash memory floats its outputs, the master (ich) takes control of fwh3 - fwh0. 10 AT49LW080/040 1966c ? flash ? 03/02 write: write operations consist of preamble, data, tar and sync fields as shown in figure 3 and described in table 6. write cycles, single byte: all devices that support fwh memory write cycles must support single-byte writes. fwh memory write cycles use the same preamble as fwh memory read cycles. for write cycles, after the preamble, the master writes the low nibble, then the high nib- ble of data. after that the master drives a tar field to give ownership of the bus to the fwh. after the second clock of the tar phase, the target device assumes the bus and begins driving sync values. a tar field to give control back to the master follows this. figure 3. fwh single-byte write waveforms note: 1. field contents are valid on the rising edge of the present clock cycle. idsel maddr msize tar tar sync clk fwh4 fwh[3:0] data preamble start table 6 . fwh write cycle clock cycle field name field contents (1) fwh[3:0] fwh[3:0] direction comments 1 start 1110b in fwh4 must be active (low) for the part to respond. only the last start field (before fwh4 transitioning high) should be recognized. the start field contents indicate an fwh memory write cycle. 2 idsel 0000b to 1111b in indicates which fwh device should respond. if the idsel (id select) field matches the value id[3:0], then that particular device will respond to subsequent commands. 3 - 9 maddr yyyy in these seven clock cycles make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most significant nibble first. 10 msize 0000b (1 byte) in the fwh only supports single-byte writes. 11 data yyyy in this field is the least significant nibble of the data byte. this data is either the data to be programmed into the flash memory or any valid flash command. 12 data yyyy in this field is the most significant nibble of the data byte. 13 tar0 1111b in then float in this clock cycle, the master (ich) has driven the bus to all 1s and then floats the bus prior to the next clock cycle. this is the firstpartofthebus ? turnaround cycle ? . 14 tar1 1111b (float) float then out the fwh takes control of the bus during this cycle. during the next clock cycle it will be driving the ? sync ? data. 15 rsync 0000b out the fwh outputs the values 0000, indicating that it has received data or a flash command. 16 tar0 1111b out then float the fwh flash memory drives fwh0 - fwh 3 to 1111b to indicate a turnaround cycle. 17 tar1 1111b (float) float then in the fwh flash memory floats its outputs, the master (ich) takes control of fwh3 - fwh0. 11 AT49LW080/040 1966c ? flash ? 03/02 output disable: when the fwh is not selected through a fwh read or write cycle, the fwh interface outputs (fwh[3:0]) are disabled and will be placed in a high-imped- ance state. response to invalid fields during fwh operations, the fwh will not explicitly indicate that it has received invalid field sequences. the response to specific invalid fields or sequences is as follows: address out of range: the fwh address sequences is seven fields long (28 bits), but only the last five address fields (20 bits) will be decoded by an 8-mbit fwh. (for a 4-mbit density, the most significant bit (fwh3) in the third address field also will be ignored.) the fwh will respond to these lower addresses, regardless of the value of the more-significant address bits. address a22 has the special function of directing reads and writes to the flash core (a22 = 1) or to the register space (a22 = 0). invalid msize field: if the fwh receives an invalid size field during a read or write operation, the internal state machine will reset and no operation will be attempted. the fwh will generate no response of any kind in this situation. invalid-size fields for a read cycle are anything but 0000. invalid-size fields for a write cycle are anything but 0000. when accessing register space, invalid field sizes are anything but 0000. once valid start, idsel, and msize fields are received, the fwh always will respond to subsequent inputs as if they were valid. as long as the states of fwh [3:0] and fwh4 are known, the response of the fwh to signals received during the fwh cycle should be predictable. the fwh will make no attempt to check the valid- ity of incoming flash operation commands. bus abort the bus abort operation can be used to immediately abort the current bus operation. a bus abort occurs when fwh4 is driven low, v il , during the bus operation; the memory will tri-state the input/output communication pins, fwh3 - fwh0 and the fwh state machine will reset. during a write cycle, there is the possibility that an internal flash write or erase operation is in progress (or has just been initiated). if the fwh4 is asserted during this time frame, the internal operation will not abort. the software must send an explicit flash command to terminate or suspend the operation. the internal fwh state machine will not initiate a flash write or erase operation until it has received the last nibble from the chipset. this means that fwh4 can be asserted as late as cycle 12 (table 6) and no internal flash operation will be attempted. hardware write-protect pins tbl and wp : two pins are available with the fwh to provide hardware write-protect capabilities. the top sector lock (tbl ) pin is a signal, when held low (active), prevents program or sector erase operations in the top sector of the device (sector 7 ? at49lw040 and sec- tor 15 ? AT49LW080) where critical code can be stored. when tbl is high, hardware write protection of the top sector is disabled. the write-protect (wp ) pin serves the same function for all the remaining sectors except the top sector. wp operates independently from tbl and does not affect the lock status of the top sector. the tbl and wp pins must be set to the desired protection state prior to starting a pro- gram or erase operation since they are sampled at the beginning of the operation. changing the state of tbl or wp during a program or erase operation may cause unpredictable results. 12 AT49LW080/040 1966c ? flash ? 03/02 if the state of tbl or wp changes during a program suspend or erase suspend state, the changes to the device ? s locking status do not take place immediately. the sus- pended operation may be resumed to successfully complete the program or erase operation. the new lock status will take place after the program or erase operation completes. these pins function in combination with the register-based sector locking (to be explained later). these pins, when active, will write-protect the appropriate sector(s), regardless of the associated sector locking registers. (for example, when tbl is active, writing to the top sector is prevented, regardless of the state of the write lock bit for the top sector ? s locking register. in such a case, clearing the write-protect bit in the register will have no functional effect, even though the register may indicate that the sector is no longer locked. the register may still be set to read-lock the sector, if desired.) 13 AT49LW080/040 1966c ? flash ? 03/02 device memory map with fwh hardware lock architecture at49lw040 sector size (bytes) address range hardware write-protect pin sa0 64k 00000 - 0ffff wp sa1 64k 10000 - 1ffff wp sa2 64k 20000 - 2ffff wp sa3 64k 30000 - 3ffff wp sa4 64k 40000 - 4ffff wp sa5 64k 50000 - 5ffff wp sa6 64k 60000 - 6ffff wp sa7 64k 70000 - 7ffff tbl AT49LW080 sector size (bytes) address range hardware write-protect pin sa0 64k 00000 - 0ffff wp sa1 64k 10000 - 1ffff wp sa2 64k 20000 - 2ffff wp sa3 64k 30000 - 3ffff wp sa4 64k 40000 - 4ffff wp sa5 64k 50000 - 5ffff wp sa6 64k 60000 - 6ffff wp sa7 64k 70000 - 7ffff wp sa8 64k 80000 - 8ffff wp sa9 64k 90000 - 9ffff wp sa10 64k a0000 - affff wp sa11 64k b0000 - bffff wp sa12 64k c0000 - cffff wp sa13 64k d0000 - dffff wp sa14 64k e0000 - effff wp sa15 64k f0000 - fffff tbl 14 AT49LW080/040 1966c ? flash ? 03/02 register-based locking and general- purpose input registers a series of registers are available in the fwh to provide software read and write locking and gpi feedback. these registers are accessible through standard addressable mem- ory space. registers: the at49lw040/080 has two types of registers: sector-locking registers and general-purpose input registers. the two types of registers appear at their respec- tive address locations in the 4 gb system memory map. sector-locking registers: the at49lw040 and the AT49LW080 have 8 (lr0 - lr7) and 16 (lr0 - lr15) sector-locking registers, respectively. each sector-locking register controls the lock protection for 64k bytes of memory as shown in table 7 (at49lw040) and table 8 (AT49LW080). the sector-locking registers are accessible through the register memory address shown in the third column of table 7 and table 8. the sector-locking registers are read/write as shown in the last column of table 7 and table 8. each sector has three dedicated locking bits as shown in table 9 and table 10. table 7 . sector-locking registers for at49lw040 register name sector size register memory address default value type lr0 64k ffb80002h 01h r/w lr1 64k ffb90002h 01h r/w lr2 64k ffba0002h 01h r/w lr3 64k ffbb0002h 01h r/w lr4 64k ffbc0002h 01h r/w lr5 64k ffbd0002h 01h r/w lr6 64k ffbe0002h 01h r/w lr7 64k ffbf0002h 01h r/w fgpi-reg ffbc0100h n/a ro 15 AT49LW080/040 1966c ? flash ? 03/02 table 8 . sector-locking registers for AT49LW080 register name sector size register memory address default value type lr0 64k ffb00002h 01h r/w lr1 64k ffb10002h 01h r/w lr2 64k ffb20002h 01h r/w lr3 64k ffb30002h 01h r/w lr4 64k ffb40002h 01h r/w lr5 64k ffb50002h 01h r/w lr6 64k ffb60002h 01h r/w lr7 64k ffb70002h 01h r/w lr8 64k ffb80002h 01h r/w lr9 64k ffb90002h 01h r/w lr10 64k ffba0002h 01h r/w lr11 64k ffbb0002h 01h r/w lr12 64k ffbc0002h 01h r/w lr13 64k ffbd0002h 01h r/w lr14 64k ffbe0002h 01h r/w lr15 64k ffbf0002h 01h r/w fgpi-reg ffbc0100h n/a ro table 9 . function of sector-locking bits bit function 7:3 reserved 2 read lock 1 = prevents read operations in the sector where set. 0 = normal operation for reads in the sector where clear. this is the default state. 1 lock-down 1 = prevents further set or clear operations to the write lock and read lock bits. lock-down can only be set, but not cleared. the sector will remain locked-down until reset (with rst or init ), or until the device is power-cycled. 0 = normal operation for write lock and read lock bits altering in the sector where clear. this is the default state. 0 write lock 1 = prevents program or erase operations in the sector where set. this is the default state. 0 = normal operation for programming and erase in the sector where clear. 16 AT49LW080/040 1966c ? flash ? 03/02 note: 1. the write lock bit must be set to the desired protection state prior to starting a program or erase operation since it is sam- pled at the beginning of the operation. changing the state of the write lock bit during a program or erase operation may cause unpredictable results. if the state of the write lock bit changes during a program suspend or erase suspend state, the changes to the sector ? s locking status do not take place immediately. the suspended operation may be resumed success- fully. the new lock status will take place after the program or erase operation completes. the individual bit functions are described in the following sections. read lock: the default read status of all sectors upon power-up is read-unlocked. when a sector ? s read-lock bit is set (1 state), data cannot be read from that sector. an attempted read from a read-locked sector will result in data 00h being read. (note that failure is not reflected in the status register). the read-lock status can be unlocked by clearing (0 state) the read-lock bit, provided the lock-down bit has not been set. the cur- rent read-lock status of a particular sector can be determined by reading the corresponding read-lock bit. write lock: the default write status of all sectors upon power-up is write-locked (1 state). any program or erase operations attempted on a locked sector will return an error in the status register (indicating sector lock). the status of the locked sector can be changed to unlocked (0 state) by clearing the write-lock bit, provided the lock-down bit is not also set. the current write-lock status of a particular sector can be determined by reading the corresponding write-lock bit. any program or erase operations attempted on a locked sector will return an error in the status register (indicating sector lock). the write-lock functions in conjunction with the hardware write-lock pins, tbl and wp . when active, these pins take precedence over the register-locking function and write- lock the top sector or remaining sectors, respectively. reading this register will not read the state of the tbl or wp pins. lock-down: when in the fwh interface mode, the default lock-down status of all sectors upon power-up is not-locked-down (0 state). the lock-down bit for any sector may be set (1 state), but only once, as future attempted changes to that sector locking register will be ignored. the lock-down bit is only cleared upon a device reset with rst or init . the current lock-down status of a particular sector can be determined by read- ing the corresponding lock-down bit. once a sector ? s lock-down bit is set, the read- and write-lock bits for that sector can no longer be modified and the sector is locked down in its current state of read and write accessibility. general-purpose inputs register: this register reads the status of the fgpi[4:0] pins on the fwh at power-up. since this is a pass-through register, there is no default value as shown in table 7 and table 8. it is recommended that the gpi pins be in the desired state before fwh4 is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. table 1 0. register-based locking value definitions data reserved data7-3 read lock, data 2 lock-down, data 1 write lock, data 0 resulting sector state (1) 00 00000 000 full access 01 00000 001 write locked. default state at power-up 02 00000 010 locked open (full access locked down) 03 00000 011 writelockeddown 04 00000 100 read locked 05 00000 101 read and write locked 06 00000 110 read locked down 07 00000 111 read and write locked down 17 AT49LW080/040 1966c ? flash ? 03/02 notes: 1. x = any valid address within the device 2. the sector must be not be write locked when attempting sector erase or program operations. attempts to issue a sector erase or byte program to a write locked sector will fail. 3. sa = sector address. any byte address within a sector can be used to designate the sector address (see page 13). 4. either 40h or 10h is recognized as the program setup. 5. following the product id entry command, read operations access manufacture and device id. see table 12. 6. aid = address used to read data for manufacture or device id 7. srd = data read from status register table 1 1. general-purpose input registers bit function 7:5 reserved 4 fgpi[4] reads status of general-purpose input pin (plcc-30/tsop-7) 3 fgpi[3] reads status of general-purpose input pin (plcc-3/tsop-15) 2 fgpi[2] reads status of general-purpose input pin (plcc-4/tsop-16) 1 fgpi[1] reads status of general-purpose input pin (plcc-5/tsop-17) 0 fgpi[0] reads status of general-purpose input pin (plcc-6/tsop-18) command definitions in (hex) command sequence bus cycles operation 1st bus cycle operation 2nd bus cycle addr data addr data read array/reset 1 write xxxx ff sector erase (2)(3) 2writesa20writesad0 byte program (2)(4) 2 write addr 40 or 10 write addr d in sector erase suspend (2) 1 write xxxx b0 program suspend (2) write sector erase resume (2) 1 write xxxx d0 program resume (2) write product id entry (5) 2 write xxxx 90 read aid (6) d out read status register 2 write xxxx 70 read xxxx srd (7) clear status register 1 write xxxx 50 18 AT49LW080/040 1966c ? flash ? 03/02 read array: upon initial device power-up and after exit from reset, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal state machine (wsm) has started a block erase or program operation, the device will not recognize the read array command until the operation is completed, unless the operation is suspended via an erase suspend or program suspend com- mand. the read array command functions independently of the v pp voltage. product identification: the product identification mode identifies the device and manufacturer as atmel. following the product id entry command, read cycles from the addresses shown in table 12 retrieve the manufacturer and device code. to exit the product identification mode, any valid command can be written to the device. the product id entry command functions independently of the v pp voltage. sector erase: beforeabytecanbeprogrammed,itmustbeerased.theerased state of the memory bits is a logical ? 1 ? . since the AT49LW080/040 does not offer a complete chip erase, the device is organized into multiple sectors that can be individu- ally erased. the sector erase command is a two-bus cycle operation. the sector whose address is valid at the second falling edge of the we will be erased, provided the given sector is not protected. successful sector erase requires that the corresponding sector ? swritelockbitbe cleared and the corresponding write-protect pin (tbl or wp )beinactive.ifsectorerase is attempted when the sector is locked, the sector erase will fail, with the reason for fail- ure in the status register. successful sector erase only occurs when v pp =v pph1 or v pph2 . if the erase operation is attempted at v pp v pph1 or v pph2 erratic results may occur. byte programming: the device is programmed on a byte-by-byte basis. program- ming is accomplished via the internal device command register and is a two-bus cycle operation. the programming address and data are latched in the second bus cycle. the device will automatically generate the required internal programming pulses. please note that a ? 0 ? cannot be programmed back to a ? 1 ? ; only an erase operation can convert ? 0 ? sto ? 1 ? s. after the program command is written, the device automatically outputs the status regis- ter data when read. when programming is complete, the status register may be checked. if a program error is detected, the status register should be cleared before cor- rective action is taken by the software. the internal wsm verification error checking only detects ? 1 ? s that do not successfully program to ? 0 ? s. reliable programming only occurs when v pp =v pph1 or v pph2 . if the program operation is attempted at v pp v pph1 or v pph2 erratic results may occur. a successful program operation also requires that the corresponding sector ? s write lock bit be cleared, and the corresponding write-protect pin (tbl or wp ) be inactive. if a pro- gram operation is attempted when the sector is locked, the operation will fail. table 12. identifier codes code address (aid) data manufacturer code 000000 1f device code at49lw040 000001 e0 AT49LW080 000001 e1 19 AT49LW080/040 1966c ? flash ? 03/02 erase suspend: the erase suspend command allows sector-erase interruption to read or program data in another sector of memory. once the sector erase process starts, writing the sector erase suspend command requests that the wsm suspend the sector erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the sector erase suspend command is written. poll- ing the status register can help determine when the sector erase operation was suspended. after a successful suspend, a read array command can be written to read data from a sector other than the suspended sector. a program command sequence may also be issued during erase suspend to program data in sectors other than the sec- tor currently in the erase suspend mode. the other valid commands while sector erase is suspended include read status regis- ter and sector erase resume. after a sector erase resume command is written, the wsm will continue the sector erase process. v pp must remain at v pph1/2 (the same v pp level initially used for sector erase) while sector erase is suspended. rst or init must also remain at v ih . sector erase cannot resume until program operations initiated during sector erase suspend have completed. program suspend: the program suspend command allows program interruption to read data in other memory locations. once the program process starts, writing the program suspend command requests that the wsm suspend the program sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the program suspend command is written. polling the status regis- ter can help determine when the program operation was suspended. after a successful suspend, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while program is suspended are read status register and program resume. v pp must remain at v pph1/2 (the same v pp level used for program) while in program suspend mode. rst or init must also remain at v ih . read status register: the status register may be read to determine when a sec- tor erase or program completes and whether the operation completed successfully. the status register may be read at any time by writing the read status register command. after writing this command, all subsequent read operations will return data from the sta- tus register until another valid command is written. the read status register command functions independently of the v pp voltage. clear status register: error flags in the status register can only be set to ? 1 ? sby the wsm and can only be reset by the clear status register command. these bits indi- cate various failure conditions. the clear status register command functions independently of the applied v pp voltage. 20 AT49LW080/040 1966c ? flash ? 03/02 notes: 1. check b7 to determine sector erase or program completion. b6 - b0 are invalid while b7 = ? 0 ? . 2. if both b5 and b4 are ? 1 ? s after a sector erase attempt, an improper command sequence was entered. 3. b3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after a sec- tor erase or program operation. b3 is not guaranteed to report accurate feedback only when v pp v pph1/2 . 4. b1 does not provide a continuous indication of write lock bit, tbl pin or wp pin values. the wsm interrogates the write lock bit, tbl pin or wp pin only after a sector erase or program operation. depending on the attempted operation, it informs the system whether or not the selected sector is locked. 5. b0 is reserved for future use and should be masked out when polling the status register. status register definition b7 write state machine status (1) 1 ready 0busy b6 erase suspend status 1 sector erase suspended 0 sector erase in progress/completed b5 erase status (2) 1 error in sector erasure 0 successful sector erase b4 program status 1 error in program 0 successful program b3 v pp status (3) 1v pp low detect, operation abort 0v pp ok b2 program suspend status 1 program suspended 0 program in progress/completed b1 device protect status (4) 1 write lock bit, tbl pin or wp pin detected, operation abort 0 unlock b0 reserved for future enhancements (5) 21 AT49LW080/040 1966c ? flash ? 03/02 a/a mux interface the following information applies only to the at49lw040/080 when in a/a mux mode. information on fwh mode (the standard operating mode) is detailed earlier in this docu- ment. electrical characteristics in a/a mux mode are provided on pages starting from page 27. the at49lw040/080 is designed to offer a parallel programming mode for faster factory programming. this mode, called a/a mux mode, is selected by having this ic pin high. the ic pin is pulled down internally in the at49lw040/080, so a modest current should be expected to be drawn (see table 1 on page 3 for further information). four control pins dictate data flow in and out of the component: r/c ,oe ,we ,andrst .r/c is the a/a mux control pin used to latch row and column addresses. oe is the data output con- trol pin (i/o0 - i/o7), drives the selected memory data onto the i/o bus, when active we and rst must be at v ih . bus operation: all a/a mux bus cycles can be conformed to operate on most auto- mated test equipment and prom programmers. notes: 1. when v pp v pplk , the memory contents can be read, but not altered. 2. x can be v il or v ih for control and address input pins and v pplk or v pph1/2 for the vpp supply pin. see the ? dc characteristics ? for v pplk and v pph1/2 voltages. 3. see table 12 on page 18 for product id entry data and addresses. 4. command writes involving sector erase or program are reliably executed when v pp = v pph1/2 and v cc =v cc 0.3v. 5. refer to ? a/a mux read-only operations ? for valid d in during a write operation. 6. v ih and v il refer to the dc characteristics associated with flash memory output buff- ers: v il min = 0.5v, v il max = 0.8v, v ih min = 2.0v, v ih max = v cc +0.5v. output disable/enable: with oe at a logic-high level (v ih ), the device outputs are disabled. output pins i/o0 - i/o7 are placed in the high-impedance state. with oe at a logic-low level (v il ), the device outputs are enabled. output pins i/o0 - i/o7 are placed in a output-drive state. row/column addresses: r/c is the a/a mux control pin used to latch row (a0 - a10) and column addresses (a11 - a18) [at49lw040], or (a11 - a19) [AT49LW080]. r/c latches row addresses on the falling edge and column addresses on the rising edge. rdy/busy : an open drain ready/busy output pin provides a hardware method of detecting the end of a program or erase operation. rdy/busy is actively pulled low dur- ing the internal program and erase cycles and is released at the completion of the cycle. bus operations mode rst oe we address v pp i/o0 - i/o7 read (1)(2)(6) v ih v il v ih xxd out output disable (6) v ih v ih v ih x x high-z product id entry (6) v ih v il v ih (3) xnote3 write (4)(5)(6) v ih v ih v il xx d in 22 AT49LW080/040 1966c ? flash ? 03/02 notes: 1. all specified voltages are with respect to gnd. minimum dc voltage on the v pp pin is -0.5v. during transitions, this level may undershoot to -2.0v for periods of <20 ns. during transitions, this level may overshoot to v cc + 2.0v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +13.0v for periods <20 ns. 3. connection to supply of v hh is allowed for a maximum cumulative period of 80 hours. 4. do not violate processor or chipset limitations on the init pin. note: 1. this temperature requirement is different from the normal commercial operating condition of flash memories. notes: 1. input leakage currents include high-z output leakage for all bi-directional buffers with tri-state outputs. 2. refer to pci spec. 3. inputs are not ? 5-volt safe. ? 4. i il may be changed on ic and id pins (up to 200 a) if pulled against internal pull-downs. refer to the pin descriptions 5. do not violate processor or chipset specifications regarding the init pin voltage. absolute maximum ratings* voltage on any pin (except v pp ) .................................-0.5v to +vcc + 0.5v (1)(2)(4) *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v pp voltage ............................................ -0.5v to +13.0v (1)(2)(3) operating conditions temperature and v cc symbol parameter test condition min max unit t c operating temperature (1) case temperature 0 +85 c v cc v cc supply voltage (3.3v 0.3v) 3.0 3.6 v fwh interface dc input/output specifications symbol parameter conditions min max units v ih (3) input high voltage 0.5 v cc v cc +0.5 v v ih (init ) (5) init input high voltage 1.35 v cc +0.5 v v il (init ) (5) init input low voltage 0.85 v v il (3) input low voltage -0.5 0.3 v cc v i il (4) input leakage current (1) 0 24 AT49LW080/040 1966c ? flash ? 03/02 notes: 1. pci specification output load is used. 2. i oh = (98.0/v cc )*(v out -v cc )*(v out +0.4v cc ). 3. i ol = (256/v cc )*v out (v cc -v out ). fwh interface ac timing specifications notes: 1. pci components must work with any clock frequency between nominal dc and 33 mhz. frequencies less than16 mhz may be guaranteed by design rather than testing. 2. applies only to rising edge of signal. clock waveform fwh interface ac input/output specifications symbol parameter condition min max units i oh (ac) switching current high 0 < v out 0.3 v cc -12 v cc ma 0.3 v cc 25 AT49LW080/040 1966c ? flash ? 03/02 notes: 1. minimum and maximum times have different loads. see pci spec. 2. for purposes of active/float timing measurements, the high-z or ? off ? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. this parameter applies to any input type (excluding clk). output timing parameters input timing parameters signal timing parameters symbol pci symbol parameter min max units t chqx t val clk to data out (1) 211ns t chqx t on clktoactive(floattoactivedelay) (2) 2ns t chqz t off clk to inactive (active to float delay) (2) 28 ns t avch t dvch t su input set-up time (3) 7ns t chax t chdx t h input hold time (3) 0ns t vspl t rst resetactivetimeafterpowerstable 1 ms t cspl t rst-clk resetactivetimeafterclkstable 100 s t plqz t rst-off reset active to output float delay (2) 48 ns t off t on t val v th v tl v test clk fwh[3:0] (valid output data) fwh[3:0] (float output data) t h v th v tl v max v test clk fwh[3:0] (valid input data) t su inputs valid 26 AT49LW080/040 1966c ? flash ? 03/02 note: 1. the input test environment is done with 0.1 v cc of overdrive over v ih and v il . timing parameters must be met with no more overdrive than this. v max specifies the maximum peak-to-peak waveform allowed for measuring the input timing. production testing may use different voltage values, but must correlate results back to these parameters. note: 1. a reset latency of 20 s will occur if a reset procedure is performed during a programming or erase operation. ac waveform for reset operation notes: 1. typical values measured at t a =+25 c and nominal voltages. 2. excludes system-level overhead. interface measurement condition parameters symbol value units v th (1) 0.6 v cc v v tl (1) 0.2 v cc v v test 0.4 v cc v v max (1) 0.4 v cc v input signal edge rate 1v/ns reset operations symbol parameter min max unit t plph (1) rst or init pulse low time (if rst or init is tied to v cc ,this specification is not applicable) 100 ns sector programming times parameter 3.3v v pp 12v v pp unit typ (1) max typ (1) max byte program time (2) 30.0 300 12.0 125 s sector program time (2) 2.0 20.0 0.8 8.0 sec sector erase time (2) 0.8 1.0 0.35 0.5 sec v ih v il rst t plph 27 AT49LW080/040 1966c ? flash ? 03/02 electrical characteristics in a/a mux mode: certain specifications differ from the previous sections, when programming in a/a mux mode. the following subsec- tions provide this data. any information that is not shown here is not specific to a/a mux mode and uses the fwh mode specifications. when the v pp voltage is v pplk , read operations from memory or reading the product id are enabled, but programming and erase functions are disabled. placing v pph1/2 on v pp enables successful sector erase and program operations. notes: 1. input leakage currents include high-z output leakage for all bi-directional buffers with tri-state outputs. 2. refer to pci spec. 3. inputs are not ? 5-volt safe. ? 4. i il may be changed on ic and id pins (up to 200 a) if pulled against internal pull-downs. refer to the pin descriptions. notes: 1. if rst is asserted when the wsm is not busy (ry/by = 1), the reset will complete within 100 ns. 2. a reset time, t phav , is required from the latter of ry/by or rst going high until outputs are valid. ac waveforms for reset operations a/a mux mode interface dc input/output specifications symbol parameter conditions min max unit v ih (3) input high voltage 0.5 v cc v cc +0.5 v v il (3) input low voltage -0.5 0.8 v i il (4) input leakage current v cc =v cc max, v out =v cc or gnd + 10 a v oh output high voltage v cc =v cc min, i oh =-2.5ma v cc =v cc min, i oh =-100a 0.85 v cc min v cc =0.4 v v v ol output low voltage v cc =v cc min, i ol =2ma 0.4 v c in input pin capacitance 13 pf c clk clk pin capacitance 3 12 pf l pin (2) recommended pin inductance 20 nh reset operations symbol parameter min max unit t plph rst pulse low time (if rst is tied to v cc , this specification is not applicable.) 100 ns t plrh rst low to reset during sector erase or program (1)(2) 20 s v ih v il v ih v il t plph t plrh ry/by rst 28 AT49LW080/040 1966c ? flash ? 03/02 note: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe may be delayed up to t chqv -t glqv after the rising edge of r/c without impact on t chqv . 3. t c =0 cto+85 c, 3.3v + 0.3v v cc . a/a mux read timing diagram a/a mux read-only operations (1)(2) symbol parameter min max units t avav read cycle time 250 ns t avcl row address setup to r/c low 50 ns t clax row address hold from r/c low 50 ns t avch column address setup to r/c high 50 ns t chax column address hold from r/c high 50 ns t chqv r/c high to output delay (2) 150 ns t glqv oe low to output delay (2) 50 ns t phav rst high to row address setup 1 s t glqx oe low to output in low-z 0 ns t ghqz oe high to output in high-z 50 ns t qxgh output hold from oe high 0 ns v ih v il r/c v ih v il oe v ih v il we v ih v il rst v oh v ol i/o v ih v il addresses t glqx t chax t avch t clax t avcl t qxgh t ghqz t glqv t chqv t phav t avav row address stable next address stable data valid high-z high-z column address stable 29 AT49LW080/040 1966c ? flash ? 03/02 notes: 1. refer to ? a/a mux read-only operations ? for valid a in and d in for sector erase or program, or other commands. 2. t c =0 cto+85 c, 3.3v 0.3v v cc . a/a mux write operations (1)(2) symbol parameter min max units t phwl rp high recovery to we low 1 s t wlwh write pulse width low 100 ns t dvwh data setup to we high (1) 50 ns t whdx data hold from we high (1) 5ns t avcl rowaddresssetuptor/c low (1) 50 ns t clax row address hold from r/c low (1) 50 ns t avch column address setup to r/c high (1) 50 ns t chax column address hold from r/c high (1) 50 ns t whwl write pulse width high 100 ns t chwh r/c high setup to we high 50 ns t vpwh v pp1,2 setuptowe high 100 ns t whgl write recovery before read 150 ns t whrl we high to ry/by going low 0 ns t qvvl v pp1,2 hold from valid srd, ry/by high 0 ns 30 AT49LW080/040 1966c ? flash ? 03/02 a/a mux write timing diagram v ih v il r/c v ih v il we v oh v ol i/o v ih v il ry/by v ih v il rst v pph1,2 v il v pp (v) v ih v il oe v ih v il addresses t qvvl t whrl t whdx t chwh t chax t clax t avch t avcl t whwl t wlwh t dvwh t vpwh t t whgl t phwl r1 c1 r2 c2 valid srd d in d in ab c d e f ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes a=v cc power-up and standby b = write sector erase or program setup c = write sector erase confirm or valid address and data d = automated erase or program delay e = read status register data f = ready to write another command 31 AT49LW080/040 1966c ? flash ? 03/02 at49lw040 ordering information i cc (ma) ordering code package operation range active standby 67 0.10 at49lw040-33jc at49lw040-33tc 32j 40t extended commercial (0 to 85 c) AT49LW080 ordering information i cc (ma) ordering code package operation range active standby 67 0.10 AT49LW080-33jc AT49LW080-33tc 32j 40t extended commercial (0 to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier package (plcc) 40t 40-lead, thin small outline package (tsop) 32 AT49LW080/040 1966c ? flash ? 03/02 packaging information 32j?plcc 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 45? max (3x) notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. common dimensions (unit of measure = mm) symbol min nom max note a 3.175 3.556 a1 1.524 2.413 a2 0.381 d 12.319 12.573 d1 11.354 11.506 note 2 d2 9.906 10.922 e 14.859 15.113 e1 13.894 14.046 note 2 e2 12.471 13.487 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ a a1 b1 e2 b e e1 e d1 d d2 33 AT49LW080/040 1966c ? flash ? 03/02 40t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40t , 40-lead (10 x 20 mm package) plastic thin small outline package, type i (tsop) b 40t 10/18/01 pin 1 0 ~ 8 d1 d pin 1 identifier b e e a a1 a2 c l gage plane seating plane l1 notes: 1. this package conforms to jedec reference mo-142, variation cd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 9.90 10.00 10.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 0.21 e 0.50 basic printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty whichisdetailedinatmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1966c ? flash ? 03/02 /xm atmel ? is the registered trademark of atmel. other terms and product names may be trademarks of others. |
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